1. Field of the Invention
The present invention is generally in the field of semiconductor chips. In particular, the present invention is in the field of inductors used in semiconductor chips.
2. Background Art
FIG. 1 shows a top view of a conventional inductor 100 on an area of a semiconductor chip. The square configuration of the inductor shown in FIG. 1 is commonly used on semiconductor chips and is referred to as a “square spiral inductor.”
The 4 metal turns of inductor 100 are referred to by numerals 104, 106, 108, and 110. Metal turns 104, 106, 108, and 110 are patterned within dielectric 102 in a manner known in the art. Thus, the areas of dielectric 102 which are flanked by metal turns 104, 106, 108, and 110 are within the electromagnetic field that will be created by metal turns 104, 106, 108, and 110. Dielectric 102 is silicon dioxide while metal turns 104, 106, 108, and 110 are aluminum or copper.
Metal turns 104, 106, 108, and 110 are patterned on one metal layer. Metal turn 110 comprises connection terminal 112. Connection terminal 112 is thus a part of inductor 100 while also functioning as a first connection terminal of inductor 100. Connection terminal 114 is also a part of inductor 100 and functions as a second connection terminal of inductor 100. However, connection terminal 114 is patterned on a different metal layer of the chip than the rest of inductor 100 to allow connection terminal 114 to cross underneath or above metal turns 104, 106, 108 and 110 of inductor 100 without shorting the metal turns together. An electrical connection between connection terminal 114 and the remainder of the metal used to fabricate metal turns 104, 106, 108, and 110 of inductor 100 is then provided by a via. Connection terminal 114 is shown in a different shade to show that it is situated on a different metal layer of the chip than the remainder of the metal used to fabricate inductor 100. The width of inductor 100 is referred to by numeral 116.
The inductance value of a square spiral inductor, such as inductor 100, is determined by the empirical equation:L≅0.38 μ0n2d  (Equation 1)where L is the net effective inductance, μ0 is the permeability of free space (μ0=4π(10−13) henrys/μm), n is the number of metal turns, d is the “spiral diameter” which is a term used to refer to width 116 of inductor 100, and 0.38 is a coefficient which is derived from the shape of the inductor.
As an example, if a circuit on a semiconductor chip required a square spiral inductor with a value of 30 nano-henrys and a pitch of one turn per 5.0 microns, the inductor would require 17 metal turns and would have a spiral diameter of 217 microns.
On-chip inductors can be used in mixed signal circuits and in RF applications such as receiver chips in wireless telephone technologies. Typical inductor values for a square spiral inductor used in such applications range from 1 to 100 nano-henrys. It can be seen from the above example that to achieve these desired values of inductance, a very large area of the chip has to be set aside for the inductor. In fact, these inductors tend to dominate the chip, leaving less area for other circuit elements. Thus, the inductor's size limits the use of on-chip inductors for RF and mixed signal circuits.
As can be seen from Equation 1, device engineers can achieve a higher inductance value by increasing the number of metal turns of the inductor. However, as the number of metal turns increases, the overall resistance of the metal turns will also increase due to the increasing length of the metal turns. The increased resistance of the metal turns results in a lower quality factor (“Q”), since the quality factor is determined by Q=L/R, where L is the inductance and R is the resistance inherent in the inductor. For a given inductance, as the resistance increases, the quality factor decreases.
Alternatively, the inductance can be increased by increasing the spiral diameter of the on-chip inductor. However, this would make the on-chip inductor even larger and would require more chip space. As explained above, square spiral inductors already dominate the chip. Therefore, there is little available space on the chip for even larger inductors.
Thus, it is seen that there are problems associated with both of the above described methods for increasing the inductance of a square spiral inductor. Either the size of the inductor will increase further by increasing the spiral diameter of the inductor, or the quality factor will go down as a result of an increased number of metal turns within a given spiral diameter of the inductor.
As a result of these problems, device engineers have been trying to achieve a higher inductance without an increase in the space occupied by the inductor on the chip and without a decrease in the quality factor of the inductor. Thus, variations in the layout of the on-chip inductor have been made to optimize the inductance value and quality factor of the inductor.
One such variation is the “hollow spiral inductor.” This on-chip inductor is similar to the square spiral inductor except that some of the metal turns at the center of the inductor are removed while the outer metal turns remain. The missing center metal turns result in lower overall resistance of the inductor and therefore a higher quality factor. Thus, by using a hollow spiral inductor instead of a square spiral inductor, a higher quality factor can be achieved for an on-chip inductor with a given spiral diameter and a given number of metal turns.
The inductance of a hollow spiral inductor is determined by the empirical equation:L≅(37.5 μ0n2a2)/(11d−14a)  (Equation 2)where L is the net effective inductance, μ0 is the permeability of free space (μ0=4π(10−13) henrys/μum), n is the number of metal turns, d is the “spiral diameter” which is substantially the same as the width of the hollow spiral inductor, a is the “spiral radius” which is arrived at by empirical calculations and is equal to or slightly less than one half of the value of the spiral diameter d, and 37.5 is a coefficient that has been determined empirically.
Similarly, other variations in the layout of on-chip inductors have been used to reduce the size of the on-chip inductor while maintaining a high inductance. However, the reduction in the size of on-chip inductors that has been achieved by these variations in the layout of the inductor has been outpaced by the continuing “scaling down” of the chip size over time. Thus, the continuing trend towards smaller chips has resulted in a need for even smaller on-chip inductors.
Another shortcoming with known inductors, such as inductor 100, is that when for various reasons it is permissible to have a smaller inductance, a “scaled down” value of inductance cannot be easily achieved by reducing the number of turns n. The reason is that when the number of turns n decreases, the inductance decreases in proportion to a decrease in the value of n2. This decrease in the value of inductance is desirable, but it is always accompanied by a degradation in the quality factor Q. The reason is that a reduction in the number of turns n causes a reduction in the value of the resistance R inherent in the inductor in linear proportion to n. As such, the quality factor Q which is given by L/R, is also reduced by a factor of n. This decrease in quality factor Q is undesirable and is a result of an attempt to reduce the value of the inductance L by simply reducing the number of turns n.
Thus, there is a serious need in the art for an on-chip inductor that occupies a smaller space on the semiconductor chip, while having at the same time a high value of inductance and a high quality factor.